This invention relates to a method for fabricating a semiconductor device, and more particularly to a method for forming an a single crystal semiconductor chip bipolar transistors, CMOS transistors, MOS capacitors, and resistors.
A semiconductor device comprising bipolar transistors and CMOS transistors which are formed on a semiconductor chip is generally called BiCMOS. The VLSI-class BiCMOS technology of prior art has been developed principally for high performance memory or logic, so that it is suitable for high integration and high speed logic. The BiCMOS technology for high performance memory and high speed, low power, high density logic of prior art is disclosed in page 212, ISSCC Digest of Technical Papers published in February, 1986 and in page 63, CICC Tech. Dig. published in May, 1986.
In order to achieve high performance digital and analog VLSI function on a single chip with prior art, there should be provided MOS elements, bipolar elements, resistors, capacitors, etc for a precise analog function and high speed, high integration digital function. However, because these elements have not been optimized for their construction and performance, there are limitations in their applications. Furthermore, a BiCMOS device of prior art having a complex self-aligned bipolar structure for high speed of element complicates the construction thereof, thus being unsuitable for mass production and cost. Alternatively, another BiCMOS device of prior art using non-self-aligned structure reduces its performance. In the bipolar structure of prior art as disclosed in pages 1010-1013, No.9, Vol. Ed-28, IEEE published in September, 1981, it is difficult to reduce the size of the structure due to the problem consisting in the scaling down of the elements. Additionally, the self-aligned bipolar technology as disclosed in pages 338-340, No.8, Vol.ED-8, IEEE provides a method for solving the problem consisting in the scaling down of the elements, but the method thereof is complicated. Further, according to the prior art as disclosed in U.S. Pat. No. 4,503,603 of L. Blossfeld, after ion implantation is performed twice into the base region and a local oxidation is done, the emitter region is formed to produce a self-aligned bipolar structure. However, since this method requires a number of heat treatments, it makes it difficult to control the shallow junction depth of the active base layer for forming a high speed and high integration bipolar transistor. Consequently, such a bipolar structure of prior art causes a problem in the method for high performance BiCMOS.